© 2019 BY ULYSSIX TECHNOLOGIES, INC.

7470 New Technology Way, Suite B  |  Frederick, MD 21703

301. 846. 4800  |  telemetry@ulyssix.com

 

Tarsus-HS-PCI-01™

33 Mbps Digital Bit Sync/Frame Sync/Decom/IRIG Time Code Reader/PCM Simulator

 

The TarsusHS-PCI-01™ Processor Board is a multi-mode PCM Processor board that contains a DSP implemented digital bit synchronizer, frame synchronizer, IRIG Class II PCM decommutator, PCM simulator and IRIG Time Code Generator/Reader. The TarsusHS™ is the most flexible and technically advanced PCM Processor board available.

 

The bit synchronizer accepts all of the IRIG 106-01 code types and has Eb/N0 rejection of better than 1 dB to the theoretical BER published curve. The input AGC accepts inputs from 75 mVpp to 10 Vpp.

 

The Ulyssix supplied Windows application software allows the user to setup each channel with easy to use GUI interface and gives indicators for loop lock, frame lock, subframe lock, AGC strength as well as soft scope outputs for the AGC data, eye pattern lock representation as well as a full frame dump display. The output of the frame synchronizer also can be dumped to the host computer hard drive for archival and data reduction applications.

 

The decommutator portion allows the user to setup parameters from 4 to 64 bits with easy to enter data processing (EU conversion) algorithms. Asynchronous embedded formats, tagged parameters, frame format identifier format changeovers are supported. All decom processed data may be displayed in tabular, strip chart, oscilloscope, FFT spectral form, dials, time digital formats, bar graph and other easy to interpret DirectX displays.

Bit Synchronizer Features

  • Full Bit Sync design using all DSP filter algorithms in FPGA technology for maximum performance capability.

  • Bit Sync programmable input rates from 1 bps up to 32 Mbps for NRZ-L/M/S, RNRZ-L, RZ and 1 bps to 16 Mbps for other code types

  • Less than 1 dB theoretical bit sync BER performance

  • Jitter tolerance up to 2 times loop bandwidth

Decommutator Features

  • Supports all IRIG Class II decommutator features with variable word length from 3 to 64 bits including format switching, parameter concatenation and embedded formats

  • High speed data transfer of user word selected channels to the PCI bus for disk storage and playback

  • On card IRIG Time code Reader for codes A, B, G, NASA36

  • Two on card DAC's for parameter analog output

 

Frame Synchronizers Features

  • Input data rate up to 33 Mbps

  • TTL Level single ended and RS-422 differential inputs

  • Programmable word lengths from 3 to 64 bits

  • Frame sync pattern programmable from 16 to 33 bits

  • Supports FCC and SFID subframe sync

  • Normal or inverted data polarity

 

PCM Simulator Features

  • Programmable output data rate from 1 bps to 33 Mbps

  • Output code types include: NRZ-L/M/S, RNRZ-L, BiP-L/M/S, RZ

  • Archived Frame Playback Capability

  • Programmable data words fixed or math function (sine wave, triangle wave, square wave, saw tooth wave, or counter