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Gryphon PCM™ Series

Multiple Bit Synchronizers w/ Frame Synchronizers, Decommutator, and IRIG Time Code Reader

 

The Gryphon PCM Multiple Bit Synchronizer/Frame Synchronizer System is a fully integrated chassis solution that may be configured for two to four bit synchronizers and frame synchronizers with an internal IRIG time code reader. The Gryphon PCM system utilizes the Ulyssix Tarsus3-02™ Dual Bit Synchronizer/Frame Synchronizer w/ IRIG time code reader product which is a state-of-the-art Digital Signal Processing (DSP) based PCM processor. The chassis is a 2U rackmount system containing dual capacitive touch screen displays with the most advanced single board computer currently available on the market.

 

The Gryphon PCM gives the ability to archive frame synced data from each channel in Ulyssix TAD format or optional Chapter 10. The internal IRIG time code reader time stamps the archived data at the beginning of each minor frame for enhanced post-processing analysis.  The Gryphon PCM can optionally broadcast PCM data via Chapter 10 UDP or TMoIP.

 

The Gryphon PCM system is controlled via the dual capacitive touchscreens or through Ethernet connection to a host computer. The Gryphon PCM displays allows for easy viewing of the bit sync lock, eye pattern, bit rate indicators for the bit syncs; frame lock and subframe lock indicators for the frame syncs; and four meters or one strip chart for decom parameters per touch screen.

 

Full diagnostic software is also included for both the bit sync and frame sync. Each frame synchronizer has a full synchronized frame dump display for quick viewing of all the data bits in the frame.

As with all the Ulyssix™ products, all Field Programmable Gate Array (FPGA) firmware upgrades to the internal Tarsus3 are done via the Gryphon PCM software interface via the USB port. 

Bit Synchronizer Features

  • Full Bit Sync design using all DSP filter algorithms in FPGA technology for maximum performance capability

  • Accepts IRIG PCM code types including: NRZ-L/M/S, RNRZ-L, Bi-P L/M/S

  • Less than 1 dB theoretical bit sync BER performance

  • Internal IRIG time code reader for DC Level IRIG-B and AM Modulated IRIG A, B, G, & NASA-36

  • Bit Sync programmable input rates from 1 bps up to 40 Mbps 

  • Integrated graphic eye pattern display for complete lock indication

Frame Synchronizer & System Features

  • Supports all IRIG Class II decommutator features with variable word length from 3 - 64 bits, format switching, parameter concatenation, and asynchronous embedded formats

  • User programmable sync search/check/lock output display strategies

  • Supports up to 1024 minor frames per major frame and 16 M bits per minor frame

  • Programmable number of frame sync bit slips and allowable sync bit errors

  • User friendly setup using dual capacitive touch screen displays or through Ethernet connection to computer running Windows GUI package

  • Fully integrated 2U rackmount chassis solution